From the first invention of integrated circuits in 1960, the number of devices on a chip has grown at an explosively increasing rate. Technologies of the semiconductor industry have been researched continuously for almost four decades. The progress of the semiconductor integrated circuits has stepped into the ULSI (ultra large scale integration) level or even a higher level. The capacity of a single semiconductor chip has increased from several thousand devices to hundreds of million devices, or even to billions of devices. Integrated circuit devices like transistors, capacitors, and connections must be greatly narrowed simultaneously to achieve such a high packing density.
The increasing packing density of the integrated circuits has generated numerous challenges to the semiconductor manufacturing process. Every device needs to be formed within a smaller area without damaging characteristics and functional operations. The demands on high packing density and low heat generation devices with good reliability and long operation life must be maintained without any degradation in their functions.
All of the challenges and demands in fabrication are expected to be solved with the four key aspects of semiconductor manufacturing, including the lithography, the film formation, the etching, and the diffusion processing technologies. The continuous increase in the packing density of the integrated circuits must be accompanied with a smaller feature size. In addition to chip area and functional considerations, all of the devices with smaller sizes must be achieved with simplified and reliable manufacturing steps to raise the yield and reduce the cost of products.
In CMOS manufacturing processes, well formation is a vital issue with the downscaling of transistor size. The undesired lateral diffusion in forming n-wells and p-wells has the effect of reducing packing density. The concept of the retrograde well was proposed for using high energy implants to place the dopants at the desired depth without further lateral diffusion. The peak of the implant can be buried at a certain depth within the substrate by adjusting implanting energy. Thus the lateral diffusion problem can be solved and the packing density of CMOS devices can be raised by forming the retrograde wells.
In addition, the high energy ion implantation is increasingly integrated into leading edge CMOS processes. The high energy ion implantation provides a simpler process in well formation than conventional diffusion processes.
L. M. Rubin et al. disclose that doped buried layers formed by MeV ion implantation are attractive alternatives to expensive epitaxial substrates for controlling latch-up in CMOS devices, in their work "Process Architectures using MeV implanted Blanket Buried Layers for Latch-Up Improvements on Bulk Silicon" (in Proceeding on Ion implantation Technology, p. 13, 1996). Two different process architecture approaches for forming effective buried layers are discussed. With the process simplifications and cost saving characteristics, the high energy ion implantation is widely employed in the leading edge CMOS processes. The largest single production application of high energy implantation is currently the implanting of retrograde wells which can replace conventional diffused wells. For future process designs, some investigators are looking at MeV implanted buried layers as a replacement for the latch-up suppression capability of epitaxial layers. A comparison between B.L./C.L. process and PAB architecture is addressed in the work.
The developing trend in the application of MeV implantation is presented by J. O. Borland in the work "Current & Emerging Production Application/Trends of MeV Technology" (in Proceeding on Ion implantation Technology, p. 17, 1996). The motivation from a manufacturing point of view is also presented for MeV twin and triple well formation including process simplification, cost reduction and improved productivity/capacity and profits. The transition from diffused twin and triple well structures to retrograde twin and triple wells eliminate typically two masking layers, high temperature well drive-ins and about 13% in total processing steps. The power of MeV in strategic cost reduction is also illustrated in the work.
J. O. Borland et al. illustrate the prospects of using doped buried layers by MeV implantation as alternatives to expensive epitaxial substrate in the work "Epi Avoidance for CMOS Logic Devices Using MeV Implantation" (in Proceeding on Ion implantation Technology, p. 21, 1996). Using MeV ion implantation and Cz bulk wafer denuding/gettering techniques, they have successfully demonstrated in bulk (non-epi) wafers superior latch-up performance and equivalent surface silicon quality (gate oxide integrity and junction leakage current) to that of p/p+ epi wafers resulting in direct retrofit replacement of epi wafers in manufacturing. The paper summarizes the various MeV epi replacement alternatives describing the advantages and limitations of each form a production implementation point of view.
However, with the outstanding characteristics and practical values in employing the MeV technology, the thick photoresist outgassing during MeV ion implantation is a major production issue.
W. J. Lee et al. illustrated the issue in the paper "Thick PhotoResist Outgassing During MeV Implantation (Mechanism & Impact on Production)" (in Proceeding on Ion implantation Technology, p. 186, 1996). It is disclosed that the generation of an ion beam and its impact into photoresist-masked wafers will have an adverse effect on the vacuum of an MeV ion implanter. They present the mechanism and effects of photoresist outgassing caused by high energy ion implantation (250 KeV to 3 MeV). Due to photoresist outgassing and its effects, production usable beam current on small process chamber can be significantly limited. Photoresist outgassing form various implant conditions are discussed. It is addressed that outgassing in the process chamber must be examined to minimize errors in dosimetry resulting from pressure increases.
Therefore, for exploiting the benefit of the high energy implantation process without the doping concentration shift issue caused by photoresist outgassing, a method of eliminating pressure variation during implantation process is highly needed. A method of eliminating photoresist outgassing in constructing CMOS vertically modulated wells by high energy ion implantation is in demand.